BLOOP: Boolean Satisifiability-based Optimized Loop Pipelining

Modulo scheduling is the premier technique for throughput maximization of loops in high-level synthesis by interleaving consecutive loop iterations. The number clock cycles between data insertions called initiation interval (II). For maximization, this value should be as low possible; therefore its minimization main optimization goal. Despite long historical existence, modulo always remained a relevant research topic over last years with many exact and heuristic algorithms available literature. Nevertheless, we are able to leverage scalability modern Boolean Satisfiability (SAT) solvers outperform state-of-the-art ILP-based latency-optimal both integer rational IIs. Our algorithm compute valid schedules whole CHStone MachSuite benchmark suites, 99% solutions being proven throughput-optimal timeout only 10 min per candidate II. various time limits, not single tested scheduler from more verified optimal or even schedule higher than our proposed approach. Using an HLS toolflow show that can effectively used generate Pareto-optimal FPGA implementations regarding resource usage.